1. Field of the Invention
This invention relates to integrated circuits, and more particularly, to a circuit and method to better protect electrical circuits such as an integrated circuit from electro-static discharge (ESD) damage.
2. Background of Related Art
Electro-static discharge (ESD) is a potentially harmful high voltage spike of electricity that can be catastrophic to one or all integrated circuits (ICs) in an electronic device. Many will appreciate the spark that occurs between ones finger and a grounded metal object after shuffling ones feet across a wool rug.
The possibility of ESD exposure has been accommodated in many conventional integrated circuits (ICs). To provide an ESD discharge path between two isolated power pins a few methods are used.
FIG. 4 shows a conventional technique for providing an electrostatic discharge (ESD) path between two power pins.
In particular, as shown in FIG. 4, back to back diodes 202a, 202b are placed between two separate power supplies (e.g., between two separate power rails PWR1 and PWR2). However, the circuit of FIG. 4 is applicable only to the limited situation where both power rails PWR1 and PWR2 operate at the same voltage level. Also, the conventional technique of FIG. 4 requires that both power supplies PWR1, PWR2 track each other such that both of the power supplies PWR1, PWR2 are ON at the same time, or both of the power supplies PWR1, PWR2 are OFF at the same time.
For instance, a user cannot turn OFF just one of the power supplies PWR1 or PWR2 to save power, since one of the two back-to-back diodes 202a, 202b will be forward biased. In this scenario the power supply that is turned OFF would actually receive power from the other power supply that is still ON, through the forward biased one of the two diodes 202a, 202b. 
FIG. 5 shows a more flexible approach to providing an electrostatic discharge path between two isolated power pins.
In particular, as shown in FIG. 5, an ESD diode 102a, 102b together with an ESD clamp circuit 101a, 101b are provided between each power supply rail PWR1, PWR2 and ground GND, respectively, providing separate protection to each power supply rail PWR1, PWR2. Thus, ESD protection relies on ESD clamps 101a and diode(s) 102a between a first power rail PWR1 connected to a first external power pin, and ground GND, and a similar ESD clamp 101b and diode(s) 102b connected between the second power rail PWR2 connected to a second external power pin, and ground GND.
FIG. 6 shows in more detail a conventional technique for providing an electrostatic discharge path between two isolated power pins shown in FIG. 5.
In particular, as shown in FIG. 6, the ESD clamp circuits 101a, 101b shown in FIG. 5 includes an RC circuit comprising a resistor 302 and capacitor 304, a series of three inverters 306-310, and an n-channel metal oxide semiconductor field effect transistor (nMOSFET) 312 driven by the output of the last inverter stage 310.
One problem associated with the conventional technique shown in FIGS. 5 and 6 is that the voltage drop across the path between power and ground may be too high such that it will cause MOSFET breakdown.
There is a need to accommodate and improve upon the current ESD designs to better avoid the danger of electro-static discharge exposure in an integrated circuit (IC) or functionally similar device.